Methods, architectures, circuits, software and systems for CRC determination
US7360142B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2004 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Aug 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprises a predetermined number of data blocks, each of the data blocks has a first fixed length, the predetermined number is an integer of at least 2, and the remainder has a length less than the predetermined number times the first fixed length; (ii) if the remainder contains at least one data bit, adding to the remainder a padding vector having a length sufficient to generate a padded data line having the predetermined number of data blocks; and (iii) performing error checking calculations on the full data lines and the padded data line. The present invention reduces the chip area and power consumption, while improving system performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.