Mixed mode verifier
US7360187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | May 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.