Technology dependent transformations for CMOS in digital design synthesis
US7360198B2 · kind B2 · utility
196Cited by
2References
6Claims
0Family size
Inventors
Key dates
| Filing date | Nov 22, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Nov 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention pertains to automated technology dependent transformations for CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and transistor-level representation of the input design specification. The transistor level type and portion to be represented at the transistor level representation is chosen by a user. The transistor sizing and evaluating the combination of said transistor-level representation and standard-cell mapping are performed iteratively to meet delay, size and power constraints for CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.