System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition
US7361585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1545
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.