Methods of forming vias in multilayer substrates
US7361593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments of the present invention illustrate methods to electrically connect multiple layers of a substrate. A first and second layer each has at least one electrical trace on a surface thereof. The substrate includes an interposer structure attached to the second layer and separating the first and second layers on at least a portion of a perimeter of the first and second layers. The method includes a steps for forming a via in the first layer, placing a first electrically conductive substance in the via, placing a second electrically conductive substance on the second layer adjacent said via, and heating an area around said via and said second electrically conductive substance until said first and second electrically conductive substances at least partially melt to form the electrical connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.