Method and apparatus for generating delays
US7362155B2 · kind B2 · utility
0Cited by
2References
16Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Feb 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the second clock signal. The method also includes generating a unit of delay based the first clock single and generating a half unit of delay based on the first and second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.