Bandwidth tunable sigma-delta ADC modulator
US7362252B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2007 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/452
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high order continuous-time Sigma-Delta Modulator (ΣΔM) is used for its high carrier-to-noise ratio (CNR) performance and low power consumption. The modulator is designed to allow zero-IF, wide-band low-pass or low-IF flexibility. The sigma-delta ADC modulator includes a receiving circuit, a plurality of loop filter transconductors, a plurality of feedforward weighting amplifiers, a first adding element, at least a local feedback circuit, a quantizer, and a feedback DAC. The local feedback circuit includes a feedback weighting amplifier and a second adding element. The feedback coefficient of the feedback weighting amplifier is tunable, and the local feedback circuits can be designed to maximize bandwidth combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.