Systems and methods for minimizing delay in a control path
US7362254B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/506
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for minimizing delay in a feedback path. In one embodiment, an analog-to-digital feedback path includes an analog-to-digital converter (ADC) configured to receive and digitize an analog signal such as an amplifier output to produce a serial digital output. A serial interface receives and parallelizes the serial digital output to produce a parallel data words that are provided to a processing unit such as a decimator. The processing unit processes the data words to produce a digital feedback signal which can then be used to modify an input signal, such as a digital audio input to the amplifier. A delay minimization subsystem is implemented in the feedback path to monitor a delay between generation of parallel data words by the serial interface and consumption of the parallel data words by the first processing unit. The delay minimization mechanism may be implemented in multiple channels of the feedback path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.