Memory cell
US7362609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Feb 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging/discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates a memory transistor that can be implemented in either silicon or Sic. The 1T cell has diode isolation to enable implementation of the architectures used in the present flash memories, and in particular the NOR and the NAND arrays. The 1T cell with diode isolation is not limited to SiC diodes. The fabrication method includes the step of forming a nitrided silicon oxide gate on the Sic substrate and subsequently carrying out the ion implantation and then finishing the formation of a self aligned MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.