Physical layer device having an analog SERDES pass through mode
US7362797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Feb 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4625
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device. Signal latency and hardware requirements are reduced by bypassing the digital portions of the SERDES devices and avoiding the parallel conversion associated with the digital portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.