Receiver including an oscillation circuit for generating an image rejection calibration tone
US7362826B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/21
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.