Interrupt control system and method for reducing interrupt latency
US7363409B2 · kind B2 · utility
3Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2006 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Apr 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable instruction to a processor in response to detecting an instruction request from the processor corresponding to an interrupt response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.