Optimizing write/erase operations in memory devices
US7363421B2 · kind B2 · utility
36Cited by
8References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Sep 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method controls write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures. The method includes: storing the erase counts of the memory blocks, creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time, and selecting for writing, out of the blocks in the memory device available for writing, the block having the lowest erase count in the chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.