Memory controller connection to RAM using buffer interface
US7363427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | May 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.