Method and apparatus to support an expanded register set
US7363476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2003 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Oct 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to accessing eight logical general integer registers. An IA-32 instruction can specify which of the eight logical general integer registers are to be accessed via 3-bit register identifier fields of the addressing mode information of the instruction. Each 3-bit register identifier can specify any of the eight logical general integer registers. An expanded logical register set (e.g., sixteen logical registers, thirty-two logical registers, sixty-four logical registers, etc.) can be accessed by remapping the addressing mode information to include at least four-bit register identifiers without defining new opcodes or defining additional instruction prefixes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.