Method and apparatus for convolutional interleaving/de-interleaving technique
US7363552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/276
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.