System for at-speed automated testing of high serial pin count multiple gigabit per second devices
US7363557B2 · kind B2 · utility
7Cited by
32References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31903
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holding device for coupling the devices to the DIB. The system also includes a rider board including a multiplexing system coupled to a control system and to the DIB, the rider board being configured to route a serial data test signal having multi-gigabit per second baud rate through one or more of the devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.