Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers
US7363563B1 · kind B1 · utility
82Cited by
11References
27Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Apr 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/243
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transmitting data. This permits data tracking circuitry of a receiver to be efficiently tested with a relatively simple loop back test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.