Flip-flop insertion method for global interconnect pipelining
US7363606B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Nov 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for inserting flip-flops in an interconnect is provided such that a cycle time constraint for the interconnect is satisfied. First of all, a flop is inserted at an initial placement at a node along a signal path of the interconnect such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net. Secondly, the initial placement of the flop is optimized such that a delay difference, defined by a downstream delay minus an upstream delay, relative to an optimal placement at a downstream node along the signal path of the net is not greater than zero. The disclosed method can also satisfy the flop stage requirement and/or a minimum number of flops requirement for an interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.