Crest factor reduction method for electronically ballasted lamps
US7365499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Apr 15, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B20/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A buck converter generates a direct current (DC) bus voltage at a buck converter output. An inverter circuit is coupled to the buck converter and configured to receive the generated DC voltage and convert the DC voltage into an alternating current (AC) voltage to drive a lamp. A power control circuit is coupled to the buck converter output and configured to provide a control voltage signal to the buck converter so that the buck converter generates the DC voltage and current of a predetermined value. A crest factor reduction circuit is coupled (a) to the buck converter output to sense a rate of change in the generated DC bus voltage, and (b) to the power control circuit to modify the control voltage signal based on the sensed rate of change in the DC bus voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.