Scrambling of the current signature of an integrated circuit
US7365523B2 · kind B2 · utility
23Cited by
5References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2006 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.