High-speed level shifter
US7365569B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2006 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a pair of differential signals. The level shifter may further include a third transistor having a drain, a source, and a gate, the drain of the third transistor directly coupled to the source of the first transistor, and the source of the third transistor directly coupled to the source of the second transistor. The gate of the third transistor is driven by a level-shifted version of an output voltage generated from the pair of differential signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.