General purpose delay logic
US7365574B2 · kind B2 · utility
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1References
18Claims
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Inventor
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.