Method and apparatus for changing parallel clock signals in a digital data transmission
US7366091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/74
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The object of the invention is to introduce an advanced method and arrangement for changing parallel data transmission connections in an assured data transmission link. According to the method of the invention, the transmission path to be received is changed, prior to the passage of errors, and the data transmission of the link remains free of errors, in case even one of the transmission paths transmits the data as error-free, even if errors occur in other paths. The error-free quality of the link is maintained also when error-free and erroneous data transmission paths are suddenly exchanged. This is realised by calculating, in the parallel outdoor units (OU) located in succession to the common indoor unit (IU), a check sum for the transmission paths, for the data located in the interval under observation, said check sum enabling error correction; by checking the correctness of the data in the receiving outdoor units or by correcting small correctable errors; and by selecting, in the receiving indoor unit, on the basis of a quality factor describing the error-free quality of paths, another more error-free transmission path, in case for instance weather conditions cause errors in th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.