High speed elastic buffer with clock jitter tolerant design
US7366207B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2003 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Sep 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/062
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver for high-speed indirect synchronous digital data transmission includes an elastic buffer receiving an incoming data stream containing embedded timing information preceding a data sequence, generating a recovered clock from the timing information, initially synchronizing the frequency of a local clock to the recovered clock, and accommodating subsequent drift between the recovered and local clocks across the duration of the data sequence while tolerating clock jitter. Received data is clocked into a FIFO buffer within the elastic buffer based on the recovered clock and read out based upon the local clock, with the buffer expanding or contracting by adjustment of an index to accommodate skew of greater than one clock period. Expansion or contraction of the FIFO buffer is disabled during periods when clock jitter is likely, such as periods immediately following an index change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.