False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method
US7366269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Nov 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data signal on a basis of the clock signal, and detecting a data pattern in which adjacent pieces of data at at least three consecutive bits differ from each other; a phase period shift detector detecting a shift between periods of phases at a change point of the data signal and a change point of the clock signal; and a determining section determining whether a false lock has occurred on a basis of results of detection of the pattern detector and the phase period shift detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.