Method of programming a co-verification system
US7366652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2005 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A co-verification system includes a computer programmed to act as a simulator for simulating behavior of a first portion of an electronic device under test (DUT) by acquiring, processing and generating data representing DUT signals. The co-verification system also includes emulation resources programmed to emulate a second portion of the DUT by receiving, processing and generating emulation signals representing DUT signals. The signals of the DUT are mapped to separate addresses within a memory space, and the simulator controls and reads states of emulation signals by writing data to and reading data from addresses of the memory space states mapped to the DUT signals the emulation signals represent. The computer and the emulation resources are also programmed to implement transactors communicating with one another through a packet routing network. The transactors set states of the emulation signals when the simulator writes to memory space addresses and for reading states of the emulation signals. The transactors monitor states of emulation signals and return data indicating those states to the simulator when the simulator reads memory space addresses mapped to DUT signals represen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.