Methods and apparatus for fast argument reduction in a computing system
US7366748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate reciprocal table in the computing device. According to another embodiment, an approximate reciprocal instruction I is operative on the computing device to use the approximate reciprocal table such that the argument reduction stage provides that—C:=I(X) and R:=X×C−1, the core approximation stage provides that p(R) is computed so that it approximates f(1+R), and the final reconstruction stage provides that T=f(1/C) is fetched and calculated if necessary, and f(X) is reconstructed based on f(X)=f([1/C]×[X×C])=g(f(1/C), f(1+R)).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.