TLB tag parity checking without CAM read
US7366829B1 · kind B1 · utility
105Cited by
66References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag parity value in a RAM portion of a TLB, using the CAM key input to generate a tag parity check value for a matched entry, and comparing the generated tag parity check value to the stored tag parity value to determine if there is a parity match or error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.