Efficient emulation instruction dispatch based on instruction width
US7366876B1 · kind B1 · utility
1Cited by
18References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.