Method and apparatus for test program generation based on an instruction set description of a processor
US7366951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2002 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Aug 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating processor test programs using a formal description of the processor's instruction set. An instruction set for a processor is formally described using a language such as ISDL. The formal description of the instruction set identifies certain characteristics of the instructions making up the instruction set. The formal description is combined with a test specification that describes desired properties of a test program by formally specifying test sequences that are to be applied to instructions having particular characteristics. A test program is generated by applying the formal test specification to the formal description of the instruction set including test sequences applicable to instructions having the particular characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.