Input termination circuitry with high impedance at power off
US7368938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Oct 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor. The gate of the third transistor is coupled to ground. The gates of the first and the second transistor are coupled to a control circuit that is adapted to provide a control signal to turn the first and the second transistor on or off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.