Data input/output circuit included in semiconductor memory device
US7368939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.