High speed transceiver with low power consumption
US7368950B2 · kind B2 · utility
7Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 16, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.