Level shifter circuit
US7368970B2 · kind B2 · utility
11Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2006 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jun 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit includes a level shifter unit and a latch unit. The level shifter unit receives two complementary input signals and converts the voltage levels of two complementary input signals. The latch unit latches the state of two output nodes before the low voltage supply is turned off. On condition that the low voltage supply is off, the level shifter circuit avoids current drainage and ensures the voltage level of the output. The invention has the advantages of small circuit size and being easy to design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.