Impedance-matched IQ network for an image rejection circuit
US7369834B2 · kind B2 · utility
5Cited by
6References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An impedance-matched IQ network includes a phase shift circuit and a back termination. The phase shift circuit includes an in-phase mixer port for receiving the in-phase signal, a quadrature-phase mixer port for receiving the quadrature phase signal, a termination port, and an output port. The back termination is coupled to the termination port of the phase shift circuit, the back termination having an impedance value substantially equal to the characteristic impedance of the phase shift circuit at the termination port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.