High-speed internal bus architecture for an integrated circuit
US7370127B2 · kind B2 · utility
7Cited by
11References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Dec 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.