Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width
US7370132B1 · kind B1 · utility
33Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | May 23, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.