Hardware efficient CRC generator for high speed communication networks
US7370263B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nd degree generator polynomial and subsequently dividing the remainder of the first division by a 32nd degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123nd degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)th byte being used in the division of the ith byte.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.