Modeling language and method for address translation design mechanisms in test generation
US7370296B2 · kind B2 · utility
16Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2004 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Jan 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.