Integrated circuit analysis method and program product
US7370308B2 · kind B2 · utility
2Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2005 |
| Grant date | May 6, 2008 |
| Priority date | — |
| Expiry date | Apr 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.