Integrated circuit anti-interference outline structure
US7372128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2003 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherein the integrated circuit anti-interference outline structure surrounds a periphery of a partial circuit within the integrated circuit and comprises a plurality of PNP structures. At a surface of the integrated circuits are two metal strips for producing a parasitic capacitance at poly layers in order to control noises within acceptable ranges. On a P-substrate therein is disposed with a deep N-well layer for connecting to an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area, and thus having noise currents overflow from a ground terminal as well as preventing the integrated circuit from invasions and leaks of electromagnetic waves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.