Arrangement of conductive pads on grid array package and on circuit board
US7372169B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.