Optimizing power consumption in amplifiers
US7372332B2 · kind B2 · utility
3Cited by
17References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/75
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods and apparatus for optimising power consumption in transistor amplifiers. The method comprises the step of adapting the amplifier characteristics of the transistor by adapting the bias impedance at the base of the transistor. The method may further comprise the step of adapting the amplifier characteristics of the transistor by adapting the quiescent collector current in the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.