Parallel digital-to-analog-converter
US7372386B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2006 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Nov 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/661
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fs including receiving the n-bit digital input data signal; generating M−1 delayed input data signals, M being the number of parallel conversions channels, the M−1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M−1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M×M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M×M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.