Flash memory device with reduced erase time
US7372738B2 · kind B2 · utility
2Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Nov 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage during the erase operation. The erase voltage generating circuit includes a discharging circuit receiving a high voltage that is regularly maintained irrespective of variations in a power voltage, and discharging the erase voltage supplied from the wordline during an erasing recovery period of the erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.