Semiconductor memory device with no latch error
US7372745B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Sep 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal. A control circuit separately generates the data control signal and the data strobe control signal. A data latch circuit latches the data signal from the data signal input circuit in response to the data strobe signal from the data strobe signal input circuit. A memory cell array has a plurality of memory cells arranged in a matrix. The latched data signal is stored in a selected one of the plurality of memory cells through the data buffer, an amplifier circuit configured to amplify a data signal read out from the selected memory cell; and an output circuit configured to output the amplified data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.