Processor power consumption control
US7373269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus provides control of power consumption of multiple central processors. The apparatus includes, sections for: measuring temperature of each central processor; calculating halt percentage for each of the central processors from measured temperatures halt percentages and a particular thread executed in each of the central processors; transitioning to a wait state in which a central processor executes another thread during a predetermined wait period or a running state in which an internal halt instruction is executed causing the central processor to halt processing in accordance with the halt percentage; and interrupting each of the central processors and causing a central processor that is halting processing to resume processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.