Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication
US7373368B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2004 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Nov 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/533
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.