Advanced execution of extended floating-point add operations in a narrow dataflow

US7373369B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Guenter Gerwig · Simmozheim, DE
• Klaus M. Kroener · Ehningen, DE

Key dates

• Filing date: Jun 4, 2004
• Grant date: May 13, 2008
• Expiry date: Nov 7, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2207/3896
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.